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1/21 october 2004 VNQ830M-E quad channel high side driver rev. 1 table 1. general features (*) per each channel n cmos compatible inputs n open drain status outputs n on state open load detection n off state open load detection n shorted load protection n undervoltage and overvoltage shutdown n loss of ground protection n very low stand-by current n reverse battery protection (**) n in compliance with the 2002/95/ec european directive description the VNQ830M-E is a quad hsd formed by assembling two vnd830m-e chips in the same so-28 package. the vnd830m-e is a monolithic device made by using | stmicroelectronics vipower m0-3 technology. the VNQ830M-E is intended for driving any type of multiple loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protects the device against overload. the device detects open load condition both in on and off state. the openload threshold is aimed at detecting the 5w/12v standard bulb as an openload fault in the on state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection table 2. order codes note: (**) see application schematic at page 10 typ e r ds(on) i out v cc VNQ830M-E 60m w (*) 6a (*) 36v so-28 (double island) package tube tape and reel so-28 VNQ830M-E vnq830mtr-e
VNQ830M-E 2/21 figure 2. block diagram overtemp. 1 v cc1,2 gnd1,2 input1 output1 overvoltage logic driver 1 status1 v cc clamp undervoltage clamp 1 openload on 1 current limiter 1 openload off 1 output2 driver 2 clamp 2 openload on 2 openload off 2 overtemp. 2 input2 status2 current limiter 2 overtemp. 3 v cc3,4 gnd3,4 input3 output3 overvoltage logic driver 3 status3 v cc clamp undervoltage clamp 3 openload on 3 current limiter 3 openload off 3 output4 driver 4 clamp 4 openload on 4 openload off 4 overtemp. 4 input4 status4 current limiter 4
3/21 VNQ830M-E table 3. absolute maximum ratings figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v p tot power dissipation t pins =25c 6.25 w e max maximum switching energy (l=1mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =10.5a) 77 mj t j junction operating temperature internally limited c t stg storage temperature - 55 to 150 c v cc 1,2 gnd 1,2 input1 status1 status2 v cc 1,2 v cc 3,4 gnd 3,4 input3 status3 v cc 3,4 v cc 3,4 output4 output4 output4 output3 output2 output2 output2 output1 v cc 1,2 output3 output3 output1 output1 input2 status4 input4 1 14 15 28 connection / pin status n.c. output input floating x x x x to ground x through 10k w resistor
VNQ830M-E 4/21 figure 4. current and voltage conventions table 4. thermal data (per island) note: 1. when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick) connected to all v cc pins. horizontal mounting and no artificial air flow note: 2. when mounted on a standard single-sided fr-4 board with 6cm 2 of cu (at least 35 m m thick) connected to all v cc pins. horizontal mounting and no artificial air flow symbol parameter value unit r thj-lead thermal resistance junction-lead per chip 20 c/w r thj-amb thermal resistance junction-ambient 60 (1) 44 (2) c/w r thj-amb thermal resistance junction-ambient (two chips on) 46 (1) 31 (2) c/w (*) v fn = v ccn - v outn during reverse battery condition i s1,2 i gnd1,2 output3 v cc1,2 gnd 1,2 input2 i out3 v cc1,2 v out4 output2 i out2 v out3 input1 i in1 status1 i stat1 output1 i out1 output4 i out4 v out2 v out1 i in2 i stat2 i stat3 i in4 i stat4 status2 status3 status4 input3 input4 v stat4 v in4 v stat3 v in3 v stat2 i in3 v in2 v stat1 v in1 i gnd3,4 gnd 3,4 i s3,4 v cc3,4 v cc3,4 v f1 (*)
5/21 VNQ830M-E electrical characteristics (8v8v 60 120 m w m w i s (**) supply current off state; v cc =13v; v in =v out =0v off state; v cc =13v; v in =v out =0v; t j =25c on state; v cc =13v; v in =5v; i out =0a 12 12 5 40 25 7 m a m a ma i l(off1) off state output current v in =v out =0v 0 50 m a i l(off2) off state output current v in =0v; v out =3.5v -75 0 m a i l(off3) off state output current v in =v out =0v; v cc =13v; t j =125c 5 m a i l(off4) off state output current v in =v out =0v; v cc =13v; t j =25c 3 m a symbol parameter test conditions min. typ. max. unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload conditions t j >t tsd 20 m s i lim current limitation 5.5v VNQ830M-E 6/21 electrical characteristics (continued) table 8. status pin (per each channel) table 9. switching (per each channel) (v cc =13v) table 10. openload detection (per each channel) table 11. logic input (per each channel) symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6ma 0.5 v i lstat status leakage current normal operation; v stat =5v 10 m a c stat status pin input capacitance normal operation; v stat =5v 100 pf v scl status clamp voltage i stat =1ma i stat =-1ma 6 6.8 -0.7 8v v symbol parameter test conditions min typ max unit t d(on) turn-on delay time r l =6.5 w from v in rising edge to v out =1.3v 30 m s t d(off) turn-off delay time r l =6.5 w from v in falling edge to v out =11.7v 30 m s dv out /dt (on) turn-on voltage slope r l =6.5 w from v out =1.3v to v out =10.4v see relative diagram v/ m s dv out /dt (off) turn-off voltage slope r l =6.5 w from v out =11.7v to v out =1.3v see relative diagram v/ m s symbol parameter test conditions min typ max unit i ol openload on state detection threshold v in =5v 0.6 0.9 1.2 a t dol(on) openload on state detection delay i out =0a 200 m s v ol openload off state voltage detection threshold v in =0v 1.5 2.5 3.5 v t dol(off) openload detection delay at turn off 1000 m s symbol parameter test conditions min typ max unit v il input low level 1.25 v i il low level input current v in =1.25v 1 m a v ih input high level 3.25 v i ih high level input current v in =3.25v 10 m a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in =1ma i in =-1ma 6 6.8 -0.7 8v v
7/21 VNQ830M-E table 12. truth table figure 5. conditions input output sense normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l v inn v statn t dol(off) open load status timing (with external pull-up) v inn v statn over temp status timing t sdl i out < i ol v out > v ol t dol(on) t j > t tsd t sdl
VNQ830M-E 8/21 figure 6. switching time waveforms table 13. electrical transient requirements on v cc pin iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. t t v outn v inn 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
9/21 VNQ830M-E figure 7. waveforms open load without external pull-up status n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc v cc >v ov status input n status n status n input n status n input n open load with external pull-up undefined overtemperature input n status n t tsd t r t j load voltage n v cc v ol
VNQ830M-E 10/21 figure 8. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / 2(i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2. v cc1,2 output2 +5v r prot output1 status1 input1 +5v status2 input2 +5v d gnd r gnd v gnd gnd1,2 gnd3,4 output3 output4 m c v cc3,4 status3 input3 status4 input4 +5v +5v r prot r prot r prot r prot r prot r prot r prot d ld note: channels 3 & 4 have the same internal circuit as channel 1 & 2.
11/21 VNQ830M-E solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. . m c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l VNQ830M-E 12/21 figure 10. off state output current figure 11. input clamp voltage figure 12. status low output voltage figure 13. high level input current figure 14. status leakage current figure 15. status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 il(off1) (ua) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.01 0.02 0.03 0.04 0.05 ilstat (ua) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
13/21 VNQ830M-E figure 16. overvoltage shutdown figure 17. turn-on voltage slope figure 18. on state resistance vs t case figure 19. i lim vs t case figure 20. turn-off voltage slope figure 21. on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 dvout/dt(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 20 40 60 80 100 120 140 160 ron (mohm) iout=2a vcc=8v; 13v & 36v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 2 4 6 8 10 12 14 16 18 20 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc (c) 200 250 300 350 400 450 500 550 600 dvout/dt(off) (v/ms) ri=6.5ohm 5 10152025303540 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 110 120 ron (mohm) iout=5a tc= - 40c tc=25c tc=150c
VNQ830M-E 14/21 figure 22. input high level figure 23. openload on state detection threshold figure 24. input hysteresis voltage figure 25. input low level figure 26. openload off state detection threshold -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 750 800 850 900 950 1000 1050 1100 1150 1200 1250 iol (ma) vcc=13v vin=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v
15/21 VNQ830M-E figure 27. maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
VNQ830M-E 16/21 so-28 double island thermal data figure 28. double island pc board table 14. thermal calculation according to the pcb heatsink area r tha = thermal resistance junction to ambient with one chip on r thb = thermal resistance junction to ambient with both chips on and p dchip1 =p dchip2 r thc = mutual thermal resistance figure 29. r thj-amb vs. pcb copper area in open box free air condition chip 1 chip 2 t jchip1 t jchip2 note on off r tha x p dchip1 + t amb r thc x p dchip1 + t amb off on r thc x p dchip2 + t amb r tha x p dchip2 + t amb on on r thb x (p dchip1 + p dchip2 ) + t amb r thb x (p dchip1 + p dchip2 ) + t amb p dchip1 =p dchip2 on on (r tha x p dchip1 ) + r thc x p dchip2 + t amb (r tha x p dchip2 ) + r thc x p dchip1 + t amb p dchip1 1 p dchip2 layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.5cm 2 , 3cm 2 , 6cm 2 ). 10 20 30 40 50 60 70 01 234567 pcb cu he atsink area (cm ^2)/is land rthj_am b (c/w) r tha r thb r thc
17/21 VNQ830M-E figure 30. so-28 thermal impedance junction ambient single pulse figure 31. thermal fitting model of a double channel hsd in so-28 pulse calculation formula table 15. thermal parameter 0.01 0.1 1 10 100 1e-04 0.001 0.01 0.1 1 10 100 1000 tim e(s) zth(c/w) 6 cm^2/ island 3 cm^2/island 0,5 cm^2/island one channel on two channels on on same chip pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r14 c13 c14 r13 tj_1 tj_2 t_amb pd3 c7 r10 c9 c10 r9 r7 r12 r11 r8 c11 c12 c8 pd4 r16 c15 c16 r15 tj_3 tj_4 r17 r18 area/island (cm 2 ) 0.5 6 r1=r7=r13=r15 (c/w) 0.05 r2=r8=r14=r16 (c/w) 0.3 r3=r9 (c/w) 3.4 r4=r10 (c/w) 11 r5=r11 (c/w) 15 r6=r12 (c/w) 30 13 c1=c7=c13=c15 (w.s/c) 0.001 c2=c8=c14=c16 (w.s/c) 5.00e-03 c3=c9 (w.s/c) 1.00e-02 c4=c10 (w.s/c) 0.2 c5=c11 (w.s/c) 1.5 c6=c12 (w.s/c) 5 8 r17=r18 (c/w) 150 z th d r th d z thtp 1 d C () + = where d t p t =
VNQ830M-E 18/21 package mechanical table 16. so-28 mechanical data figure 32. so-28 package dimensions symbol millimeters min typ max a 2.65 a1 0.10 0.30 b 0.35 0.49 b1 0.23 0.32 c 0.50 c1 45 (typ.) d 17.7 18.1 e 10.00 10.65 e 1.27 e3 16.51 f 7.40 7.60 l 0.40 1.27 s 8 (max.)
19/21 VNQ830M-E figure 33. so-28 tube shipment (no suffix) figure 34. tape and reel shipment (suffix tr) all dimensions are in mm. base q.ty 28 bulk q.ty 700 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 a c b base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions
VNQ830M-E 20/21 revision history date revision description of changes oct. 2004 1 - first issue
21/21 VNQ830M-E information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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